A chip package serves to protect a bare chip, reduce a density of chip contacts, and provide a good heat dissipation effect for the chip. A common packaging process is to install the chip onto a package carrier, and contacts of the chip are electrically connected to the package carrier. Therefore, distribution of the contacts of the chip can be rearranged through the package carrier to cope with a contact distribution of a next stage external device.
As light weight, compactness, and high efficiency have become typical requirements of consumer electronic and communication products, chip packages should provide superior electrical properties, small overall volume, and a large number of I/O ports. Package carriers used in these chip packages often have multiple metal layers that can be electrically connected through interconnections. As the size of chip packages decreases, these interconnections can become smaller and more closely spaced, which can increase the cost and complexity of packaging processes.
It is against this background that a need arose to develop the package carriers, the package structures, and processes described herein.